module SPI_4Byte_Transmitter
(
    // 系统信号
    input wire i_Clk,
    input wire i_Rst_L,
    
    // 控制信号
    input wire i_Start,           // 开始传输脉冲
    output reg o_Busy,           // 传输进行中
    output reg o_Done,           // 传输完成脉冲
    
    // 数据输入
    input wire [31:0] i_Data_32bit, // 32位数据（4字节）
    
    // SPI Master接口
    output wire [7:0] o_TX_Byte,
    output reg o_TX_DV,
    input wire i_TX_Ready,
    input wire i_RX_DV,
    input wire [7:0] i_RX_Byte,
    
    // SPI接口
    output wire o_SPI_CS          // SPI片选信号
);

// 状态定义
parameter [2:0] 
    IDLE        = 3'b000,
    ASSERT_CS   = 3'b001,
    SEND_BYTE0  = 3'b010,
    SEND_BYTE1  = 3'b011,
    SEND_BYTE2  = 3'b100,
    SEND_BYTE3  = 3'b101,
    DEASSERT_CS = 3'b110;

reg [2:0] current_state, next_state;

// 内部信号
reg [1:0] byte_counter;
reg [31:0] data_shift_reg;
reg cs_internal;

// 状态寄存器
always @(posedge i_Clk or negedge i_Rst_L) begin
    if (!i_Rst_L) begin
        current_state <= IDLE;
    end else begin
        current_state <= next_state;
    end
end

// 下一状态逻辑
always @(*) begin
    case (current_state)
        IDLE: begin
            if (i_Start) 
                next_state = ASSERT_CS;
            else
                next_state = IDLE;
        end
        
        ASSERT_CS: begin
            next_state = SEND_BYTE0;
        end
        
        SEND_BYTE0: begin
            if (i_TX_Ready & ~o_TX_DV) 
                next_state = SEND_BYTE1;
            else
                next_state = SEND_BYTE0;
        end
        
        SEND_BYTE1: begin
            if (i_TX_Ready & ~o_TX_DV) 
                next_state = SEND_BYTE2;
            else
                next_state = SEND_BYTE1;
        end
        
        SEND_BYTE2: begin
            if (i_TX_Ready & ~o_TX_DV) 
                next_state = SEND_BYTE3;
            else
                next_state = SEND_BYTE2;
        end
        
        SEND_BYTE3: begin
            if (i_TX_Ready & ~o_TX_DV) 
                next_state = DEASSERT_CS;
            else
                next_state = SEND_BYTE3;
        end
        
        DEASSERT_CS: begin
            next_state = IDLE;
        end
        
        default: next_state = IDLE;
    endcase
end

// 数据移位寄存器
always @(posedge i_Clk or negedge i_Rst_L) begin
    if (!i_Rst_L) begin
        data_shift_reg <= 32'h0;
    end else if (current_state == IDLE) begin
        data_shift_reg <= i_Data_32bit;
    end else if ((i_TX_Ready & ~o_TX_DV) && (current_state == SEND_BYTE0 || current_state == SEND_BYTE1 || current_state == SEND_BYTE2)) begin
        data_shift_reg <= {data_shift_reg[23:0], 8'h00}; // 左移8位
    end
end

// 字节计数器
always @(posedge i_Clk or negedge i_Rst_L) begin
    if (!i_Rst_L) begin
        byte_counter <= 2'b00;
    end else if (current_state == IDLE) begin
        byte_counter <= 2'b00;
    end else if (i_TX_Ready && (current_state == SEND_BYTE0 || current_state == SEND_BYTE1 || current_state == SEND_BYTE2)) begin
        byte_counter <= byte_counter + 1'b1;
    end
end

// TX数据输出
// always @(posedge i_Clk or negedge i_Rst_L) begin
//     if (!i_Rst_L) begin
//         o_TX_Byte <= 8'h00;
//     end else begin
//         case (current_state)
//             SEND_BYTE0: o_TX_Byte <= data_shift_reg[31:24];
//             SEND_BYTE1: o_TX_Byte <= data_shift_reg[31:24];
//             SEND_BYTE2: o_TX_Byte <= data_shift_reg[31:24];
//             SEND_BYTE3: o_TX_Byte <= data_shift_reg[31:24];
//             default:    o_TX_Byte <= 8'h00;
//         endcase
//     end
// end
assign o_TX_Byte = data_shift_reg[31:24];

// TX数据有效信号
always @(posedge i_Clk or negedge i_Rst_L) begin
    if (!i_Rst_L) begin
        o_TX_DV <= 1'b0;
    end else begin
        // 在状态转换时产生TX_DV脉冲
        case (current_state)
            ASSERT_CS:  o_TX_DV <= 1'b1;
            SEND_BYTE0: o_TX_DV <= (i_TX_Ready & ~o_TX_DV) ? 1'b1 : 1'b0;
            SEND_BYTE1: o_TX_DV <= (i_TX_Ready & ~o_TX_DV) ? 1'b1 : 1'b0;
            SEND_BYTE2: o_TX_DV <= (i_TX_Ready & ~o_TX_DV) ? 1'b1 : 1'b0;
            SEND_BYTE3: o_TX_DV <= 1'b0; // 最后一个字节不需要再触发
            default:    o_TX_DV <= 1'b0;
        endcase
    end
end

// CS信号控制
always @(posedge i_Clk or negedge i_Rst_L) begin
    if (!i_Rst_L) begin
        cs_internal <= 1'b1; // 默认CS为高（不选中）
    end else begin
        case (current_state)
            IDLE:       cs_internal <= 1'b1;
            ASSERT_CS:  cs_internal <= 1'b0;
            SEND_BYTE0: cs_internal <= 1'b0;
            SEND_BYTE1: cs_internal <= 1'b0;
            SEND_BYTE2: cs_internal <= 1'b0;
            SEND_BYTE3: cs_internal <= 1'b0;
            DEASSERT_CS:cs_internal <= 1'b1;
            default:    cs_internal <= 1'b1;
        endcase
    end
end

assign o_SPI_CS = cs_internal;

// 忙信号
always @(posedge i_Clk or negedge i_Rst_L) begin
    if (!i_Rst_L) begin
        o_Busy <= 1'b0;
    end else begin
        o_Busy <= (current_state != IDLE);
    end
end

// 完成信号
always @(posedge i_Clk or negedge i_Rst_L) begin
    if (!i_Rst_L) begin
        o_Done <= 1'b0;
    end else begin
        o_Done <= (current_state == DEASSERT_CS);
    end
end

endmodule